报告题目：Compact Model for Multi-Gate FET（多门常效应管的压缩模式）

报告人姓名：沃松涛博士（美国三星电子）

报告时间：2018-5-21，9：30-10：30

报告地点：平板显示楼二楼大会议室

承办单位：新型显示教育部重点实验室

报告人简介：

Dr. Wo is senior device engineer of Samsung Austin Semiconductor. He received his master degree at Fudan University and PH.D. degree in materials sciencce engineering from University of Vermont in 2011. He worked as compact model engineer for 3 years in IBM and later joined Samsung electronics since 2013.

Dr. Wo's expertise is compact modeling and device engineering of cutting edge FIN FET technology on 14nm and 10nm node.

报告摘要：

The adoption of Silicon-on-Insulator (SOI) substrates for the manufacturing of mainstream semiconductor products such as microprocessors has given SOI research an unprecedented impetus. In the past, novel transistor structures proposed by SOI scientists were often considered exotic and impractical, but the recent success of SOI in the field of microprocessor manufacturing has finally given this technology the credibility and acceptance it deserves.

The classical CMOS structure is reaching its scaling limits and “end-ofroadmap” alternative devices are being investigated. Amongst the different types of SOI devices proposed, one clearly stands out: the multigate fieldshape with a gate electrode that controls the flow of current between The International Technology Roadmap for Semiconductors (ITRS) There exists a number of textbooks on SOI technology. Some of these books tackle the subject of multigate FETs, but there is no book that contains a comprehensive description of the physics, technology and circuit applications of this new class of devices.